ULSI circuits include semiconductor memories as various kinds of RAMs and ROMs, optoelectronic devices as displays, e.g., active matrix liquid crystal displays, and sensors, as contact sensors and projected image sensors. These ULSI circuits can have as many as a million or more individual pixels, display cells, sensor cells, or memory cells, over an area of less than one tenth of a square meter, e.g., from about 0.6 square meter or more. Deposited or grown semiconductor ULSI's may contain 10 or more pixels, memory cells, or sensor cells per square millimeter. Each such individual cell has many resistors, diodes, and capacitors, and active devices, such as field effect transistors, and junction transistors. Thus, a ULSI may contain up to 40 million or more such individual devices, with each device having a feature size of as small as one micron.
These ultra large scale integrated circuits are fabricated by various methods including both epitaxial growth and deposition, by CVD and plasma processes. One typical method of fabricating these devices is the sequential deposition of amorphous semiconductor alloy layers to form, for example, large area diodes. These large area diodes may then be subsequently patterned, e.g., by lithographic processes, to form many individual diodes. Depositions may be accomplished by plasma assisted chemical vapor deposition, as disclosed, for example, in U.S. Pat. Nos. 4,226,898 and 4,485,389 to Stanford R. Ovshinsky and Masa Izu. As described by Ovshinsky and Izu, a plurality of semiconductor layers are successively deposited on a substrate, following which a top layer of metal is deposited. At least the top metal layer is then patterned using conventional photoresist mask and etching techniques, following which the semiconductor layer or layers may be likewise patterned, also using conventional photoresist mask and etching techniques.
An alternative method of fabricating thin film semiconductor ULSI circuits comprises depositing the semiconductor layers on a substrate, patterning the semiconductor layers with one large pattern, depositing the top layer of the metal, and then patterning the top metal layer with another pattern.
ULSI circuits can also be fabricated by sequentially combining several related techniques, e.g., deposition and/or epitaxial techniques in sequence with etching techniques. These techniques are especially useful in fabricating ULSI circuits with individual devices of semiconductor and semiconductor alloy materials, especially amorphous, microcrystalline, or polycrystalline semiconductor alloys of silicon or germanium. Examples of such individual devices include diodes, Schottky barrier diodes, non-linear threshold switches, field effect transistors, junction transistors, capacitors, and the like as well as linear devices as resistors.
These sequential steps have particular application to thin film semiconductor devices employing so called mesa structures, as found, for example in thin film large area distributed memories, displays, and sensors. "Mesa structure" refers to a structural or topographical feature of the device as characterized by one or more superimposed patterned semiconductor layers being elevated relative to the surrounding features of the device by the use of one or more steeply sloped or substantially vertical sidewalls. As described by Meera Vijan, John McGill, and Paul Day in U.S. Pat. No. 4,680,085 issued July 14, 1987, for A Method of Manufacturing Thin Film Semiconductor Devices, and specifically incorporated herein by reference, it is possible to fabricate large area, ULSI, active matrix liquid crystal displays having a plurality of diodes per pixel, e.g., two to four diodes per pixel. These large area, ULSI, active matrix liquid crystal displays are described in U.S. patent application Ser. Nos. 573,004, now abandoned, and 675,941, now abandoned, respectively filed on Jan. 23, 1984 and Dec. 3, 1984. The processes can also be used to produce ULSI circuits comprising non-linear threshold switch devices of the type described in U.S. patent application Ser. No. 603,852 now U.S. Pat. No. 4,667,189 issued May 1987 to Willem den Boer, J. Scott Payson, and Zvi Yaniv for Programmable Semiconductor Switch For A Display Matrix Or The Like And Method Of Making The Device and in U.S. patent application Ser. No. 679,770 filed Dec. 10, 1984 now U.S. Pat. No. 4,698,627 a continuation-in-part of said U.S. patent application Ser. No. 603,852. Similarly, ULSI circuits can contain n-pi-n and p-nu-p threshold devices using punch through technology described in U S. patent application Ser. No. 720,767 filed Apr. 8, 1985, now abandoned; and in the corresponding European Laid Open Patent Application 198346 of Subhendu Guha for Solid State Threshold Devices as well as two dimensional imaging devices of the type disclosed in U.S. patent application Ser. No. 713,928 filed Mar. 20, 1985 now U.S. Pat. No. 4,675,739 issued June 23, 1987 to Vincent Cannella, Clive Catchpole, John Keem, Louis Swartz, and Zvi Yaniv for Integrated Radiation Sensing Array. The disclosures of all of the aforementioned U.S. Patents and U.S. Patent Applications are specifically incorporated herein by reference.
As described by Meera Vijan, John McGill and Paul Day, above, the ULSI fabrication method comprises the steps of depositing one or more semiconductor layers on a substrate, forming a top contact metal mask over portion of a semiconductor layer, and thereafter removing the unwanted portions of semiconductor layers around a portion of semiconductor alloy material protected by the mask. The unwanted semiconductor alloy material is removed by an etching process in which a source of reactive ions etch away the unwanted portion of the semiconductor alloy material and the mask acts to prevent etching of those portions of the semiconductor layer which underlie the mask. As described by Vijan, et al. the etching is performed in a plasma reaction chamber in which ion bombardment is normal to the surface of the substrate. Consequently lateral etching of the semiconductor layers is eliminated and the resulting mesa structure possesses smooth sidewalls free of voids or overhangs. Moreover, the edges of the top metal contact mask are aligned with the walls of the underlying semiconductor layers. Vijan, et al. reports that the use of carbon tetrafluoride as the process gas during the etching, in the substantial absence of oxygen, provides particularly desirable results.
Following the processing of the mesa structure to repair ion damage and neutralize any contaminants on the sidewalls thereof, an insulative layer may be deposited over and around the mesa structure. This insulative layer preferably makes continuous contact with the mesa structure sidewalls, thus obviating possible voids. In a subsequent step, a via, preferably having sloped sidewalls, is formed through the insulative layer to the top metal contact mask. Thereafter, a layer of metallization is applied to the device using conventional masking and etching techniques. The remaining unetched metallization fills the via to make contact with the upper metal contact mask and forms an electrical lead which is connected to the top layer of the mesa structure. The bottom semiconductor layer of the mesa structure is connected to a bottom electrical contact lead which may be deposited on the substrate, e.g., before the mesa structure is formed.
The address lines in ULSI circuit are deposited by similar techniques. Typically, the x address lines, the y address lines, and the individual non-linear devices of the ultra large surface area ULSI's have a feature size of about 10 microns or less. As noted above, other large area, ULSI circuits as used in a display, sensor, or ROM, may have up to 40 million or more individual non-linear active devices incorporated therein. Testing of either all of the individual devices, or of at least all of the individual cells or elements containing a plurality of devices is necessary in order to avoid carrying improperly manufactured ULSI circuits through the complete manufacturing process, especially in the case of ULSI circuits having transparent conductive elements.